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USENIX Technical Program - Paper - Proceedings of the Third Symposium on Operating Systems Design and Implementation   
[Technical Program]
Next: Motivation
Optimizing the Idle Task and Other MMU TricksCort Dougan Paul Mackerras Victor Yodaiken
January 4, 1999 Abstract:
In highly cached and pipelined machines,
operating system performance, and aggregate user/system performance,
is enormously sensitive to small changes in cache and TLB hit rates.
We have implemented a variety of changes in the memory management
of a native port of the Linux operating system to the
PowerPC architecture in an effort to improve performance. Our
results show that careful design to minimize the OS caching footprint,
to shorten critical code paths in page fault handling, and to otherwise
take full advantage of the memory management hardware can have dramatic
effects on performance. Our results also show that the operating system
can intelligently manage MMU resources as well or better than hardware can
and suggest that complex hardware MMU assistance may not be the most
appropriate use of scarce chip area. Comparative benchmarks
show that our optimizations result in kernel performance that is
significantly better than other monolithic kernels for the same
architecture and highlight the distance that micro-kernel designs will
have to travel to approach the performance of a reasonably
efficient monolithic kernel.
Next: Motivation Cort Dougan 1999-01-04 |
This paper was originally published in the
Proceedings of the Third Symposium on Operating Systems Design and Implementation, February 22-25, 1999, New Orleans, Louisiana, USA
Last changed: 26 Mar 2002 ml |
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