Memory Behavior of an X11 Window System
J. Bradley Chen
School of Computer Science
Carnegie Mellon University
Abstract
We used memory reference traces from a DEC Ultrix system running the
X11 window system from MIT Project Athena and several freely available
X11 applications to measure different aspects of memory system
behavior and performance. Our measurements show that memory behavior
for X11 workloads differs in several important ways from workloads
more traditionally used in cache performance studies. User
instruction cache behavior is a major component in overall memory
system delays, with significant competition within and between address
spaces. User TLB miss rates are up to a factor of two higher than
other ill-behaved integer workloads. Write-buffer stalls, data cache
behavior, and uncached memory reads can be problematic for
microbenchmarks, but they are not an issue for the realistic
applications we tested.
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