Performance Estimation

An implementation of the AES encryption algorithm with a key length of 128 bits on Infineon´s SLE66P (8051 based) security controller family, cf. [Inf2], combined together with Infineon´s recently developed modular arithmetic coprocessor Spiridon, cf. [Inf1] (which has no AND or RotWord operation), is approximately two times faster than an optimized 8051 based implementation, and requires only 16 bytes of internal RAM memory. Most importantly, this implementation greatly benefits from the high physical attack security offered by the Spiridon coprocessor, which will be described in another publication. However, we expect an implementation using an optimal modular arithmetic coprocessor with all the operations described at the beginning of the present paper by at least a factor of four faster than the implementation on Infineon´s Spiridon.